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Chips, Memory, and Power | Pat Gelsinger

October 9, 2026

AI Summary

5 min read

Chips, Memory, and Power | Pat Gelsinger

Pat Gelsinger, former CEO of Intel and VMware, now a general partner at Playground Global, sat down with a16z's Ragu Raguraam and Guido Abenzeller to discuss the next bottlenecks in AI infrastructure. Drawing on his career that began when he joined Intel at age 18 as a technician, Gelsinger argues that while AI is making chip design dramatically faster, the hard constraints have shifted to manufacturing timelines, memory bandwidth, power delivery, and energy capacity. The conversation ranges from the history of chip design tools to the physics of stacking memory, the future of optical networking, and what virtualization looks like when agents—not humans—are the primary users.

When AI Makes Design Easy, the Bottleneck Moves

Gelsinger draws a direct parallel between the 486 processor he helped design and today's AI-driven chip design tools. In the late 1980s, there was no commercial EDA industry. His team invented their own hardware description language, built their own compiler, and worked with Berkeley researchers to create the first automated placement and routing tools. "We created EDA to some degree," he says. Now, AI tools are doing something similar: making the logic design phase dramatically faster.

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What you'll learn

  • 1 (02:30) **Welcome and Pat’s Early Career** - Pat Gelsinger joins Ragu Raguraam and Guido Abenzeller to discuss his path from a 16-year-old at tech school to becoming a key engineer at Intel.
  • 2 (06:20) **The 486 and the Birth of Modern Chip Design Tools** - Pat explains how the 486 project forced his team to invent foundational EDA tools because no commercial industry existed yet.
  • 3 (07:49) **Will AI Create a Similar Design Revolution?** - The conversation shifts to whether today’s AI-driven chip design is a comparable turning point to the 486 era.
  • 4 (09:33) **The New Bottleneck: Manufacturing Time** - Pat identifies the critical bottleneck created by faster AI-powered design: the physical time to build a chip.
  • 5 (12:05) **Memory: The "Hideous" Bottleneck** - Pat calls HBM a "hideous memory" that is currently the best option, and explains why memory innovation is overdue.
  • 6 (13:48) **The Explosion of AI Chips: Temporary or Permanent?** - Pat debates whether the current proliferation of ~100 AI inference accelerator chips is sustainable.
  • 7 (19:26) **Controversy: Will AI Make Heterogeneity Easier?** - Guido challenges Pat, suggesting that AI agents writing software kernels overnight could lower the barrier for supporting many hardware architectures.

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Show Notes

a16z's Raghu Raghuram and Guido Appenzeller sit down with Playground Global General Partner and former Intel CEO Pat Gelsinger to discuss the next wave of semiconductor innovation and the physical constraints shaping the AI buildout.

Drawing on his experience designing Intel's 386 and 486 processors, Pat explains how AI could transform chip design, but also why faster design alone won't solve the industry's biggest problems. They examine the bottlenecks in manufacturing, memory bandwidth, advanced packaging, and power, and why today's explosion of specialized AI chips may eventually consolidate around a smaller number of architectures.

They also discuss the potential for new memory technologies, the shift from copper to optical networking, and why energy capacity could become a major constraint on AI growth. Finally, they revisit Pat's VMware years to ask what virtualization might look like when infrastructure is built for agents rather than humans.


Resources:

Follow Pat Gelsinger on X:  https://x.com/PGelsinger

Follow Raghu Raghuram on X: https://x.com/RaghuRaghuram

Follow Guido Appenzeller: https://x.com/appenz

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